New OSMU output stage ideas
Added 2018-08-12 12:51:10 +0000 UTCSorry for the lack of activity here, this thing is keeping me terribly busy *_*
OSMU introduction if you haven't seen: https://youtu.be/H-BiphMqp5g?t=267
Previous attempt https://imgur.com/epvoqIG had a lot of problems. Comment if you can spot any :)
This attempt is based on this discrete apex power op amp hybrid https://www.apexanalog.com/resources/products/mp108u.pdf
It took a much smarter person than myself to see that there are problems with this design too: The MOSFET bias voltage has to be adjusted with changes in temperature, otherwise there will be a crowbar current straight through both MOSFETs.
But by tediously summing up the FETs Vgs,th tempcos vs those of the BJTs someone has shown that this arrangement is actually temperature compensated as can be expected from the manufacturer. Only the components have to be coupled thermally which should be easy since I still want to bolt these modules on a big heat sink.
A working example of voltage and current clamping can be seen in older Keithley SMU service manuals like https://doc.xdevs.com/doc/Keithley/236_237/Keithley_236_237_Source_Measure_Unit_SMU_Service_Manual_and_schematics.pdf
But I am hesitating to build that discretely, the circuit just keeps growing uncontrollably: https://imgur.com/a/f9oKjpl And it might even need transconductance amplifiers for IC1C and IC1D. The old LT1970 would be neater all-in-one solution. On which side of the isolation barrier should I put it?
For now I think I'll just order some new boards and see what happens?
